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ICM102A CIF CMOS sensor Data Sheet Version 1.0 July 2002
ICM102A CIF CMOS image sensor Data Sheet V1.0 July 2002
IC Media Corporation 545 East Brokaw Road San Jose, CA 95112, U.S.A. Phone: (408) 451-8838 Fax: (408) 451-8839 Email: Sales@IC-Media.Com Web Site: www.ic-media.com IC Media Technology Corporation 6F, No. 61, ChowTze Street., NeiHu District Taipei, Taiwan, R.O.C. Phone: 886-2-2657-7898 Fax: 886-2-2657-8751 Email: Ap.Sales@IC-Media.Com.tw Web Site: www.ic-media.com.tw
Important notice: This document contains information of a new product. IC Media Corp. reserves the right to make any changes without further notice to any product herein to improve design, function or quality and reliability. No responsibility is assumed by IC Media Corp. for its use, nor for any infringements of patents of third parties that may result from its use.
(c)2000, 2001, 2002 IC Media Corporation & IC Media Technology Corp. web site: http://www.ic- media.com/ web site: http://www.ic- media.com.tw/ page 1
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ICM102A CIF CMOS sensor Data Sheet Version 1.0 July 2002
Features
* * * * * * * * * * * * * * * 101,376 (352x288) pixels, CIF format, used with 1/7" optical system Progressive readout Output data format: 8-bit raw data Control interface: SIF Electronic exposure control On-chip 9-bit ADC Correlated double sampling Video mode at frame rate of 30/15/10/6/5/3/2/1 fps Dead column removal Flash light control Power down mode Automatic optical black compensation Support both master and slave mode Mirror image Single 3.3 V power supply
General Description
ICM-102A is a single-chip digital color imaging device. It incorporates a 352x288 sensor array (362x298 in physical layout) operating at 1 ~ 30 frames per second in progressive manner. Each pixel is covered by a color filter, which formed a so -called Bayer pattern. Correlated double sampling is performed by the internal ADC and timing circuitry. The raw data can be adjusted by the digital gain for all pixels, or be adjusted separately for the 4 Bayer pattern pixels. The output format is 8-bit raw data which can be fed to other DSP, color processing, or compression chips.
Application
* * * * * * * * * * * Digital camcorder Digital still camera Video phone Video conferencing Video mail Video cellular phone PC camera Security system Visual toy Industrial image capture/analysis Environment monitor system
Key Parameters
* * * Number of Active Pixels: 352x288 Number of Physical Pixels: 362x298 Frame Rate: 30/15/10/6/5/3/2/1 fps
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ICM102A CIF CMOS sensor Data Sheet Version 1.0 July 2002
* * * * * * * * * * * * * * * * Pixel Size: 6.0 m x 6.0 m Sensor Area: 2.2 mm x 1.8 mm Main Clock Frequency: up to 12 MHz Exposure Time: 83 s (@ 30 fps, 1 line, 12 MHz) ~ 164 s (@ 1 fps, 65,535 lines, 12 MHz) RGB Gain:1/256 to 8 for individual Bayer pattern pixels Sensitivity: 2.0 V/lux-sec (555 nm) Quantum Efficiency: 38% (555 nm) Dynamic Range: 53 dB (analog), 48 dB(digital) Digital Gain: 1 ~ 64 x @ 2N for all pixels Fill Factor: 28% RGB Gain: 11 bits format 3.8(default), 1/256 to 8 for individual Bayer pattern pixels S/N Ratio: 40 dB @ 75% full signal level Sensitive to infrared illumination source Power Supply: 3.3 V Power Requirement: 25 mA (@ 30fps, 12 MHz) Package: Ceramic LCC48, Plastic LCC48, Shrunk Plastic LCC48, miniature lens module (dimension 8mm x 8mm x 5.8mm)
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ICM102A CIF CMOS sensor Data Sheet Version 1.0 July 2002
1. Pin Assignment
Pin # 14 11 12 13 34 36 32 33 2 1 10 16 8 48 47 Name CLKSEL CLKIN XIN XOUT PCLK OEN SIFID MSSEL SCL SDA POWERDN RSET RSTN DOUT[7] DOUT[6] Class* D, I, N D, I, N A, I A, O D, O D, I, N D, I, N D, I, U D, I/O D, I/O D, I, N A, I D, I, U D, O D, I/O D, I/O D, I/O D, I/O D, I/O D, I/O D, I/O Function Clock source selection. 0: internal oscillator, 1: CLKIN External clock source Oscillator in Oscillator out Pixel clock output Output enable. 0: enable, 1: disable Lsb of SIF slave address SIF master/slave selection. 0: slave, 1: master SIF clock SIF data Power down control, 0: power down, 1: active Resistor to ground = 39 K @ 12 MHz main clock Chip reset, active low Data output bit 7 Data output bit 6; if pulled up/down, the initial value of TIMING_CONTROL_LOW[2] (VSYNC polarity) is 1/0 Data output bit 5; if pulled up/down, the initial value of TIMING_CONTROL_LOW[1] (HSYNC polarity) is 1/0 Data output bit 4; if pulled up/down, the initial value of AD_IDL[3] (Sub ID) is 1/0 Data output bit 3; if pulled up/down, the initial value of AD_IDL[2] (Sub ID) is 1/0 Data output bit 2; if pulled up/down, the initial value of AD_IDL[1] (Sub ID) is 1/0 Data output bit 1; if pulled up/down, the initial value of AD_IDL[0] (Sub ID) is 1/0 Data output bit 0; if pulled up/down, the synchronization mode is in master/slave mode which requires HSYNC and VSYNC operating in output/input mode Horizontal sync signal Vertical sync signal Flash light control Analog ramp output Sensor analog power Sensor analog ground Sensor digital power Sensor digital ground
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46
DOUT[5]
44 41 39 38 37
DOUT[4] DOUT[3] DOUT[2] DOUT[1] DOUT[0]
3 5 35 15 7, 31 9, 30 19 17
HSYNC VSYNC FLASH RAMP VDDA GNDA VDDD GNDD
D, I/O D, I/O D, O A, O P P P P
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ICM102A CIF CMOS sensor Data Sheet Version 1.0 July 2002
4, 43 6, 45 40 42 18 VDDK GNDK VDDO GNDO GNDS P P P P P Digital power Digital ground Pad power Pad ground Substrate ground
Class Code: A - Analog signal, D - Digital signal, I - Input, O - Output, P - Power or ground, U - Internal pull-up, N - Internal pull-down
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ICM102A CIF CMOS sensor Data Sheet Version 1.0 July 2002
2. Functional Description
ICM-102A is a single-chip digital color imaging device. It includes a 352x288 sensor array, 352 column-level ADC, and correlated double sampling circuitry. All the programmable parameters are set by writing into the SIF interface which can address the register file consisting of 8-bit registers. The output format is 8-bit raw data, together with horizontal and vertical sync signals.
I2C Interface
Sensor Array 352x288
Column-Level ADC
Timing Control
Correlated Double Sampling
Digital Gain
RGB Output Format Control
Figure 1. Block diagram
2.1 Image Array
The image array consists of 352x288 pixels. Each pixel has a light sensitive photo diode and a set of control and transfer transistors. At the beginning of the cycle, a row of pixels is pre-charged to its maximum value. Then the row is exposed to light for several lines worth of time and sampled by the ADC. A "Correlated Double Sampling (CDS)" process is performed with subtracting the reset value (sampled right before sampling the signal) from the signal value. The purpose of CDS is to eliminate the point-wise fixed pattern noise (FPN). The output of CDS is approximately proportional to the amount of received light, ranging from 0 to 255.
2.2 Color Filter
Each pixel is covered by a color filter. They form the Bayer Pattern as shown in Figure 3. (Row 0, Column 0) is covered by a Red filter, (Row 0, Column 1) and (Row 1, Column 0) by Green filters, and (Row 1, Column 1) by a Blue filter. Since each pixel only gets part of the frequency band, the data need further
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ICM102A CIF CMOS sensor Data Sheet Version 1.0 July 2002
processing (i.e., color interpolation and color correction) in order to approximate the full visible spectrum.
R G R G
G B G B
R G R G
G B G B
R G R G
G B G B
R G R G
G B G B
Figure 2. Color filter Bayer pattern
2.3 Exposure and Gain Control
The brightness of the scene may change by a great amount that renders the captured image either over-exposed or under-exposed. To accommodate for different brightness, the user may change the exposure time by adjusting the AD_EXPOSE_TIMEH, and AD_EXPOSE_TIMEL. The exposure time is measured in terms of the time to read out one line of data, which is equal to 83.3 s (assuming the line length is 500 @ 12 MHz). If the number of lines per frame is set at 400 (the default), the exposure time can vary from 1 to 399 lines. In addition, users can adjust bit 7 to 5 of register AD_COL_BEGINH to digitally boost the output value by 1 to 64 times @ 2N for all the pixels. Furthermore, users can adjust registers AD_M1_L, AD_M1_H, AD_M2_L, AD_M2_H, AD_M3_L, AD_M3_H, AD_M4_L, AD_M4_H, to optimize the individual R/G1/G2/B gain (default at 3.8 format for 1/256 to 8) of the 4 Bayer pattern pixels separately.
2.4 Output Format
During normal operation, the output format is 8-bit raw data that ranges from 0 to 255. It may be used for off-chip color processing or compression. A typical configuration is to connect ICM-102A to a USB/Compression combo chip. When operated at 30 fps, the PCLK is 6 MHz when the input main clock is 12 MHz. In addition to the data pins, the chip also output VSYNC, HSYNC, BLANK, and PCLK. The length and polarity of VSYNC and HSYNC can be adjusted through registers. The line and frame timing can be adjusted through registers AD_WIDTH and AD_HEIGHT.
2.5 SIF Interface
Register programming is through SIF interface (SCL and SDA pins). The 7-bit SIF device address is 0x20 by default, but the last bit can be configured by the SIFID pin. ICM-102A can operate in either SIF master mode or slave mode right after power up, depending on the pull-up or pull-down of the MSSEL pin. When MSSEL is pulled low during power-up, ICM-102A's SIF interface is operated as an SIF slave device, waiting to be controlled by an external SIF master such as a microprocessor. When MSSEL is pulled high during power-up, the SIF interface is first acting as an SIF master device trying to read from an external SIF EEPROM. After that, it will fall back to behave like an SIF slave.
3. SIF Registers
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ICM102A CIF CMOS sensor Data Sheet Version 1.0 July 2002
Addres s 0x00 Name PART_CONTROL Default 0 Description Processing control [0] 0: normal mode, 1: single frame mode [1] Slope adjustment enable [2] Exposure time control, writing a 1 will activate the new value set in AD_EXPOSE_TIME, when read back from it, 0 means either the exposure time change is finished (in video mode) or the entire frame is transmitted (in single frame mode), 1 means either the exposure time change is still in progress (in video mode) or the frame is yet to finish (in single frame mode) [6:3] Frame rate, 0: 30 fps 1: 20 fps 2: 15 fps 3: 12 fps 4: 10 fps 5: 6 fps 6: 5 fps 7: 4 fps 8: 3 fps 9: 2 fps 10: 1 fps [7] Latent change, writing a 1 means the changed latent registers now starts taking effect, when the entire operation is done, the read back value of this bit will change from 1 to 0. Timing control [0] Reserved. [1] HSYNC polarity, 0: active low, 1: active high, the initial value is determined by DOUT[6] [2] VSYNC polarity, 0: active low, 1: active high, the initial value is determined by DOUT[5] [3] Auto dark correction enable [4] Reserved [6] Flash polarity, 0: active low, 1: active high [7] Blank polarity, 0: active low, 1: active high [8] Reserved [10] Capture: when in single frame mode, writing a 1 here will start a frame capture [11] Dead column removal mode, 0: color, 1: black-and-white [12] Reserved [13] Reserved [9:0] Frame width
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0x01 0x02
TIMING_CONTROL_LO W TIMING_CONTROL_HIG H
0x0011
0x0C
AD_WIDTHL
0x01F4
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ICM102A CIF CMOS sensor Data Sheet Version 1.0 July 2002
0x0D 0x0E 0x0F 0x10 0x11 AD_WIDTHH AD_HEIGHTL AD_HEIGHTH AD_COL_BEGINL AD_COL_BEGINH (500) 0x0190 (400) 0x0064 (100) [15:0] Frame height, should not be less than AD_ROW_BEGIN + 298 [9:0] Beginning of active line in terms of column position [10] Mirror image enable [15:13] Digital gain 0: 1 1: 2 2: 4 3: 8 4: 16 5: 32 6: 64 [15:0] Beginning of active frame in terms of row position [9:0] End of horizontal sync in terms of column position [15:0] End of vertical sync in terms of row position [15:0] Exposure time in terms of number of rows [10:0] Gain coefficient (G1) , in unsigned 3.8(default) format [10:0] Gain coefficient (R) , in unsigned 4.7(default) format [10:0] Gain coefficient.(B) , in unsigned 5.6(default) format [10:0] Gain coefficient.(G2) , in unsigned 6.5(default) format [4:0] Output format 0: default, unsigned 3.8 format 1: default, unsigned 4.7 format 2: default, unsigned 5.6 format 3: default, unsigned 6.5 format 0-7, 12-31: 8-bit raw data 8: control signals 9: row address 10: column address 11: sensor raw data [9:0] Dead column #0 in terms of real sensor array [9:0] Dead column #1 in terms of real sensor array [9:0] Dead column #2 in terms of real sensor array [9:0] Dead column #3 in terms of real sensor array [3:0] Sub ID, Read from pins DOUT[4:1]
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0x14 0x15 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x52
AD_ROW_BEGINL AD_ROW_BEGINH AD_HSYNC_ENDL AD_HSYNC_ENDH AD_VSYNC_ENDL AD_VSYNC_ENDH AD_EXPOSE_TIMEL AD_EXPOSE_TIMEH AD_M1_L AD_M1_H AD_M2_L AD_M2_H AD_M3_L AD_M3_H AD_M4_L AD_M4_H AD_INOUTSEL
0x000A (10) 0x0040 (64) 0x0003 (3) 0x018f (399) 0x100 (256) 0x100 (256) 0x100 (256) 0x100 (256) 0
0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x82
AD_DEAD0L AD_DEAD0H AD_DEAD1L AD_DEAD1H AD_DEAD2L AD_DEAD2H AD_DEAD3L AD_DEAD3H AD_IDL
0x03FF 0x03FF 0x03FF 0x03FF 0x1020
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ICM102A CIF CMOS sensor Data Sheet Version 1.0 July 2002
0x83 AD_IDH (4176) during reset [15:4] Device ID, default 0x102, can be configured using SIF [15:0] Flash light begin position in terms of rows [15:0] Flash light end position in terms of rows [7:0] When auto dark correction is disabled, serve as the subtrahend for dark correction [9:0] When auto slope adjustment is turned on, if the slope counter exceeds this value, the ramp will become steeper Reserved Reserved Reserved [9:0] Current frame width, read only [15:0] Current frame height, read only [9:0] Current column beginning position, read only [9:0] Current row beginning position, read only [9:0] Current HSync end position, read only [15:0] Current VSync end position, read only [7:0] Current part control setting, read only [9:0] Current wave table beginning point, read only [9:0] Current wave table end point, read only
0x84 0x85 0x86 0x87 0x90 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0Xaf 0XB0 0xB1
AD_FLASH_BEGINL AD_FLASH_BEGINH AD_FLASH_ENDL AD_FLASH_ENDH AD_DARK_DATA AD_SLOPE_END_TIMEL AD_SLOPE_END_TIMEH AD_WT_BEGINL AD_WT_BEGINH AD_WT_ENDL AD_WT_ENDH AD_SUB_EN_TIMEL AD_SUB_EN_TIMEH AD_WIDTHL_C AD_WIDTHH_C AD_HEIGHTL_C AD_HEIGHTH_C AD_COL_BEGINL_C AD_COL_BEGINH_C AD_ROW_BEGINL_C AD_ROW_BEGINH_C AD_HSYNC_ENDL_C AD_HSYNC_ENDH_C AD_VSYNC_ENDL_C AD_VSYNC_ENDH_C AD_PART_CONTROL_C AD_WT_BEGINL_C AD_WT_BEGINH_C AD_WT_ENDL_C AD_WT_ENDH_C
0x012A (298) 0x013E (318) 0 0x0155 (341) 0 0x03FC (1020) 0x01DA (474) 0x01F4 (500) 0x0190 (400) 0x0064 (100) 0x000A (10) 0x0040 (64) 0x0003 (3) 0x06 (6) 0 0x03FC (1020)
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ICM102A CIF CMOS sensor Data Sheet Version 1.0 July 2002
4. Electrical Characteristics 4.1 DC Characteristics Symbol VCCA VINA VOUTA TSTG Parameter Absolute Power Supply Absolute Input Voltage Absolute Output Voltage Storage Temperatu re Operating Power Supply Operating Input Voltage Operating Temperatu re Operating Current @ VCC=3.3 V, 25 C Input Low Current Input High Current Tri-state Leakage Current Input Capacitanc e Rating Typical Unit V V V
Minimum -0.3 -0.3 -0.3 0
Maximum 3.8 VCC + 0.3 VCC + 0.3
25
65
C V V
VCC VIN TOPR IDD
3.0 0 0
3.3
3.6 VCC
25 30
55
C mA
IIL IIH IOZ CIN
-1 -1 -10 3
1 1 10
A A A pF
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ICM102A CIF CMOS sensor Data Sheet Version 1.0 July 2002
COUT CBID Output Capacitanc e Bi-direction al Buffer Capacitanc e Input Low Voltage Schmitt Input Low Voltage Input High Voltage Schmitt Input High Voltage Output Low Voltage Output High Voltage Input Pull-up/do wn Resistance 3 3 pF pF
VIL VILS
0.3 * VCC 1.1
V V
VIH VIHS VOL
0.7 * VCC 1.8 0.4
V V V
VOH RL
2.4 50
V K
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ICM102A CIF CMOS sensor Data Sheet Version 1.0 July 2002
4.2 Timing
Reset Timing
>2 CLKIN
RSTN VDD CLKIN
Unstable clock >2 CLKIN 0.9 * Vcc
Pixel Timing PCLK DOUT[7:0] HSYNC VSYNC
Use PCLK rising edge to latch data
Default Line Timing
500 PCLK 100 5 352 5 38
HSYNC DOUT[7:0]
64
Column 105~ 456 is valid
Default Frame Timing
400 Rows 10 298 92
VSYNC HSYNC DOUT[7:0]
0
3
1
2
9
10
11
307
308
399
0
Row 15 ~ 307 is valid
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ICM102A CIF CMOS sensor Data Sheet Version 1.0 July 2002
4.3 Pixel Clock Duty Cycle
In different frame rate mode (controlled by PART_CONTROL[6:3]), the duty cycle (high time / clock period) of the PCLK signal is described in the following table: Frame Rate 30 20 15 12 10 6 5 4 3 2 1 Duty Cycle 50.0% 66.6% 50.0% 60.0% 50.0% 50.0% 50.0% 53.3% 50.0% 50.0% 50.0%
5. Mechanical Information
Figure 3. Shrunk Plastic LCC48 Packaging
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ICM102A CIF CMOS sensor Data Sheet Version 1.0 July 2002
6. Ordering Information
Part number for different package: Description Shrunk Plastic LCC48 package, CIF resolution sensor (3.3V) Part Number ICM-102Asa
IC Media Corporation 545 East Brokaw Road San Jose, CA 95112, U.S.A. Phone: (408) 451-8838 Fax: (408) 451-8839 Email: Sales@IC-Media.Com Web Site: www.ic-media.com
IC Media Technology Corporation 6F, No. 61, ChowTze Street., NeiHu District Taipei, Taiwan, R.O.C. Phone: 886-2-2657-7898 Fax: 886-2-2657-8751 Email: Sales@IC-Media.Com.tw Web Site: www.ic-media.com.tw
(c)2000, 2001, 2002 IC Media Corporation & IC Media Technology Corp. web site: http://www.ic- media.com/ web site: http://www.ic- media.com.tw/ page 15
7/24/2002

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